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IS31FL3189 integrated silicon solution, inc. ? www.issi.com rev.a, 11/14/2011 1 audio modulated led driver november 2011 general description the IS31FL3189 is an led driver with an audio synchronization mode that virtually eliminates the need of real time software processing for led lighting effects. the out0~9 can be operated at 4 basic modes: audio synchronization mode, top-down scan mode, constant current mode, combination of audio synchronization and top-down scan mode. each of the out0~2, out7~9 is a constant current sink pulse width modulated in 256 steps, featuring one shot programming mode and interface intensity control mode for rgb lighting effects. the output current is user selectable to be one of 5 levels, 17.5ma, 28.9ma, 38.9ma, 46.7ma or 66.5ma (typical). at 38.9ma the IS31FL3189 outputs require only 0.4v of headroom voltage. in one shot programming mode, the timing characteristics for output current - current ramping up, holding, ramping down and off time, can be adjusted individually so that each output can independently maintain a pre-established pattern without requiring any additional interface activity, thus saving valuable system resources. in interface intensity control mode, the pwm duty cycle of each output can be independently programmed and controlled in 256 steps to simplify color mixing. applications ? cellular phones ? mp3/mp4/cd/minidiskplayers ? digital picture frame/toys features ? 10 outputs each with 38.9ma at 0.4v headroom. ? 2 independently controlled, 6 channels of 256 steps pwm rgb led drivers with programmable brightness and blinking patterns for led?s lighting effects ? fully programmable operating modes: ? audio synchronization mode ? audio synchronization +top-down scan mode ? top-down scan mode ? constant current mode ? one shot programming mode with gamma correction ? interface intensity control mode with 256 steps current level setting for rgb lighting effects ? rgb blink/not blink with audio mode ? each outputs enable/disable individually ? programmable parameter setting: ? audio gain setting ? top-down scan mode output current setting ? top-down scan mode scan rate setting ? rgb mode output current setting ? programmable output current level settings ? for anode-common leds ? vdd range: 3.0v to 5.5v ? package: qfn-20, 3mm 3mm typical application circuit figure 1 typical application circuit
IS31FL3189 integrated silicon solution, inc. ? www.issi.com rev.a, 11/14/2011 2 pin configuration package pin configurations (top view) qfn-20 20 19 18 6 7 8 9 10 17 16 out3 out4 gnd out5 out6 sck gnd in c_filt r_ext pin description no. pin description 1 sdb shutdown, pull to gnd for shutdown mode. 2 vdd power supply. 3~7, 9~13 out0 ~ out9 led outputs. 8,17 gnd ground. 14 c s chip select, active is low. 15 sdi input serial data for data shift resister. 16 sck input clock for data shift on rising edge. 18 in audio signal input. 19 c_filt low pass filter input. 20 r_ext external resistor (r ext ) connect pin to regulate the output current. thermal pad connect to gnd. copyright ? ? ? 2011 ? integrated ? silicon ? solution, ? inc. ? all ? rights ? reserved. ? issi ? reserves ? the ? right ? to ? make ? changes ? to ? this ? specification ? and ? its ? products ? at ? any ? time ? without ? notice. ? issi ? assumes ? no ? liability ? arising ? out ? of ? the ? application ? or ? use ? of ? any ? information, ? products ? or ? services ? described ? herein. ? customers ? are ? advised ? to ? obtain ? the ? latest ? version ? of ? this ? device ? specification ? before ? relying ? on ? any ? published ? information ? and ? before ? placing ? orders ? for ? products. ? integrated ? silicon ? solution, ? inc. ? does ? not ? recommend ? the ? use ? of ? any ? of ? its ? products ? in ? life ? support ? applications ? where ? the ? failure ? or ? malfunction ? of ? the ? product ? can ? reasonably ? be ? expected ? to ? cause ? failure ? of ? the ? life ? support ? system ? or ? to ? significantly ? affect ? its ? safety ? or ? effectiveness. ? products ? are ? not ? authorized ? for ? use ? in ? such ? applications ? unless ? integrated ? silicon ? solution, ? inc. ? receives ? written ? assurance ? to ? its ? satisfaction, ? that: ? a.) ? the ? risk ? of ? injury ? or ? damage ? has ? been ? minimized; ? b.) ? the ? user ? assume ? all ? such ? risks; ? and ? c.) ? potential ? liability ? of ? integrated ? silicon ? solution, ? inc ? is ? adequately ? protected ? under ? the ? circumstances
IS31FL3189 integrated silicon solution, inc. ? www.issi.com rev.a, 11/14/2011 3 ordering information industrial range: -40c to +85c order part no. package qty/reel IS31FL3189-qfls2-tr qfn-20, lead-free 2500
IS31FL3189 integrated silicon solution, inc. ? www.issi.com rev.a, 11/14/2011 4 absolute maximum ratings supply voltage, v dd - 0.3v ~ +6.0v voltage at any input pin - 0.3v ~ v dd +0.3v junction temperature, t jmax - 40c ~ +150c storage temperature range, tstg - 65c ~ +150c operating temperature ratings ? 40c ~ +85c junction temperature 150c solder information, vapor phase (60s) infrared (15s) 215c 220c note: stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress rating s only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of th e specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. electrical characteristics the following specifications apply for v dd = 5v, unless otherwise noted. limits apply for t a = 25c. ( note 1 ) symbol parameter condition min. typ. max. unit v dd supply voltage 3.0 5.5 v i dd quiescent power supply current v sdb = v dd 0.7 1.0 ma i sd shutdown current v sdb = gnd 0.04 1.0 a software shutdown v sdb = vdd 1.7 3 a i out average output current audio synchronization mode v ds = 0.6v, gain = 12db, r ext = 1k ? vin = 0.5vp-p square wave 6.9 ma top-down scan mode, audio input gain register with default value v ds = 0.6v, r ext = 1k ? when out x turned on 11.4 ma interface intensity control mode pwm duty cycle = 0xff,v ds = 0.6v out0~out2, out7~out9 38.9 ma v hr current sink headroom voltage i out = 38.9ma 400.0 mv sck, sdi,cs _____ , sdb logic electrical characteristics v in(0) logic ?0? input voltage v dd = 3v 0.4 v v in(1) logic ?1? input voltage v dd = 5.5v 1.4 v i in(0) logic ?0? input current v in = 0v 5.0 na (note 2) i in(1) logic ?1? input current v in = v dd 5.0 na (note 2)
IS31FL3189 integrated silicon solution, inc. ? www.issi.com rev.a, 11/14/2011 5 digital input switching characteristics (note 2) symbol parameter condition min. typ. max. unit f ck sck frequency 1.0 mhz t ch sck high time 200 ns t cl sck low time 200 ns t dh sdi setuptime 50 ns t ds sdi high time 50 ns t css cs _____ to sck rise setup time 250 ns t cscp cs _____ rising edge to sck rising edge 200 ns t csh cs _____ pulse high time 300 ns note 1: production testing of the device is performed at 25c. functional operation of the device and parameters specified over other temperature range, are guaranteed by design, characterization and process control. note 2: guaranteed by design.
IS31FL3189 integrated silicon solution, inc. ? www.issi.com rev.a, 11/14/2011 6 spi interface the IS31FL3189 contains a 16bit spi interface to access the internal data and control registers of the device (see registers definitions). this module is used to receive the commands transmitted by mcu. the 16-bit serial interface uses three pins, sdi, sck and c s to enter data, table 1 shows the functions of these three pins. data read is not available and data entered must be 16 bits. table 2 shows the structure of the 16-bit command word and figure 2 shows the timing diagram of this serial interface. when the spi block is idle, the mcu must maintain high. for the mcu to transmit data to the IS31FL3189, c s must be pulled low and remain low during the time of command transmission. the first 8 bits are address bits and the remaining 8 bits are data bits. table 1 serial pins table 2 16-bit serial data format a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 msb register address (see table 3) lsb msb data lsb sck sdi cs a7 d7 d0 t css t ds t dh t csh t cscp t ch t cl a0 figure 2 interface timing signal name attribute direction description sck edge triggered mcu-> is31fl31 89 serial bus clock sdi level mcu -> is31fl31 89 serial data c s active low mcu -> is31fl31 89 spi bus selection
IS31FL3189 integrated silicon solution, inc. ? www.issi.com rev.a, 11/14/2011 7 registers definition the IS31FL3189 device contains 32 registers, which are li sted in table 3. communication to the IS31FL3189 is via the serial interface. the command consists of an 8-bit address word followed by an 8-bit data word. table 3 register function map address name function ta bl e default 00h configuration configure the operation mode 4 0000 0001 01h audio input gain set audio input gain 5 0000 0000 02h rgb mode set rgb mode 6 03h rgb gain1 set rgb current 7 04h out0_pwm set out0 pwm duty cycle 8 0000 0000 ( note 1) 05h out1_pwm set out1 pwm duty cycle 8 06h out2_pwm set out2 pwm duty cycle 8 07h out7_pwm set out7 pwm duty cycle 8 08h out8_pwm set out8 pwm duty cycle 8 09h out9_pwm set out9 pwm duty cycle 8 0ah out0_t0 out0 holdoff delay time 9 0000 0000 (note 2) 0bh out1_t0 out1 holdoff delay time 9 0ch out2_t0 out2 holdoff delay time 9 0dh out7_t0 out7 holdoff delay time 9 0eh out8_t0 out8 holdoff delay time 9 0fh out9_t0 out9 holdoff delay time 9 10h out0_t1&t2 out0 ramping up time and hold time 10 11h out1_ t1&t2 out1 ramping up time and hold time 10 12h out2_ t1&t2 out2 ramping up time and hold time 10 13h out7_ t1&t2 out7 ramping up time and hold time 10 14h out8_ t1&t2 out8 ramping up time and hold time 10 15h out9_ t1&t2 out9 ramping up time and hold time 10 16h out0_t3&t4 out0 ramping down time and off time 11 17h out1_t3&t4 out1 ramping down time and off time 11 18h out2_t3&t4 out2 ramping down time and off time 11 19h out7_t3&t4 out7 ramping down time and off time 11 1ah out8_t3&t4 out8 ramping down time and off time 11 1bh out9_t3&t4 out9 ramping down time and off time 11 1ch update update data of register 0ah~1bh xxxx xxxx (note 3) 1dh out7-0_en enable out7~0 12 1111 1111 (note 4) 1eh out9-8_en enable out9~8 13 11xx xxxx (note 4) 1fh town-down_en top-down scan mode enable 14 00000000 20h rgb gain2 set rgb current 15 00000000
IS31FL3189 integrated silicon solution, inc. ? www.issi.com rev.a, 11/14/2011 8 note: 1. in interface intensity control mode, the pwm duty cycle is defined by input data set in register 04h-09h. 2. in one shot programming mode, the pwm duty cycle is defined by t0-t4.t0 is holdoff delay time.t1 is gamma-corrected ramping up time.t2 is hold time.t3 is gamma-corrected ramping down time.t4 is off time. the section embedded breathing rgb lighting effect s in application discuss more about time registers. 3. write any 8 bit data to the update register after set the value of t0~t4 to update the value of them. 4. in out7-0_en register, out7 is controlled by the msb. for example, we send 0111 1111 to out7-0_en register to disable out7 but other output channels are enabled. in out9-8_en register, d7 controls the out9, d6 controls the out8. table 4 configuration register (00h) bit d7:d6 d5 d4 d3:d1 d0 name mod sdrgb1 sdrgb2 sr ssd default 00 0 0 000 1 the configuration register controls IS31FL3189 operation mode. mod IS31FL3189 mode selection 00 top-down scan plus audio synchronization mode 01 audio synchronization mode 10 top-down scan mode sdrgb1 rgb1 (out0~out2) pwm control mode enable 0 disable 1 enable sdrgb2 rgb2 (out7~out9) pwm control mode enable 0 disable 1 enable sr scan rate of top-down scan mode selection 000 normal rate, ? t=22ms 001 normal rate2 010 normal rate4 011 normal rate/2 100 normal rate/4 ssd software shutdown mode enable 0 chip enable 1 chip disable table 5 audio input gain register (01h) bit d7:d5 d4:d2 d1:d0 name ag rc - default 000 000 00 the audio input gain register sets the audio input gain of IS31FL3189 and the current of scan mode ag audio gain adjust bits 000 0db 001 3db 010 6db 011 9db 101 12db 110 16db 111 20db 100 24db rc current of scan mode selection 000 11ma 001 17ma 010 24ma 011 30ma 100 40ma 101 9ma 110 7ma 111 5ma table 6. rgb mode register (02h) bit d7 d6 d5 d4 d3:d0 name bk1 bk2 mrgb1 mrgb2 - default 0 0 0 0 0000 when pwm control mode is aroused (d5 or d4 of 00h is set to 1), the rgb mode register selects the operation mode. bk1 rgb1 (out0~out2) blinking with audio enable 0 disable 1 enable bk2 rgb2 (out7~out9) blinking with audio enable 0 disable 1 enable mrgb1 rgb1 (out0~out2) mode selection 0 interface intensity control mode 1 one shot programming mode mrgb2 rgb2 (out7~out9) mode selection 0 interface intensity control mode 1 one shot programming mode
IS31FL3189 integrated silicon solution, inc. ? www.issi.com rev.a, 11/14/2011 9 table 7 rgb gain1 register (03h) bit d7 d6 d5 d4 d3 d2 d1 d0 name bg1 bg2 rgb1_c rgb2_c default 0 0 0 0 0 0 0 0 when pwm control mode is aroused (d5 or d4 of 00h is set to 1), the rgb gain1 register selects the gain and maximum current. bg1 audio gain of rgb1 when blinking with audio 00 0db 01 3db 10 6db 11 -3db bg2 audio gain of rgb2 when blinking with audio 00 0db 01 3db 10 6db 11 -3db rgb1_max maximum current for rgb1 (typ.) 00 38.9ma 01 46.7ma 10 66.5ma 11 28.9ma rgb2_max maximum current for rgb2 (typ.) 00 38.9ma 01 46.7ma 10 66.5ma 11 28.9ma default the outputs each with 38.9ma current capability, they are adjustable. the rgb current register allows the maximum output current to be scaled as indicated in table above. the IS31FL3189 provides for a maximum current ranging as high as 66.5ma and as low as 28.9ma. care must be taken so as not to exceed the maximum allowable power dissipation for the device. table 8 outx_pwm register (04h~09h) bit d7:d0 name pwm default 0000 0000 in interface intensity control mode, the pwm duty cycle is defined by input data set in register 04h-09h. out0_pwm register acts when d5 of rgb mode register is set to 0, the value of out0_pwm register decides the average output current of out0, the average output current may be computed using the formula, ? ? ? 7 0 out 2 * 256 9 . 38 i n n ma where n stands for the set bit sequence number, for d4, n=4. an example: d7~d0=10110101, i out =38.9ma*(2 0 +2 2 +2 4 +2 5 +2 7 )/256 =27.4ma. see table 14 in application information for more. out1 ~out2, out7 ~out9 pwm register are the same as out0 pwm register. time registers in one shot programming mode, the pwm duty cycle is defined by t0-t4. by programming different values of t0~t4 for the different outputs, out0~out2, out7~out9, many different combinations led effects can be created. t0 t1 t2 t3 t1 t4 full cycle figure 3 timing parameters the complete waveform period consists of the summation of all times t1~t4.
IS31FL3189 integrated silicon solution, inc. ? www.issi.com rev.a, 11/14/2011 10 table 9 outx_t0 register (0ah~ 0fh) bit d7:d4 d3:d0 name t0 - default 0000 0000 t0 is the holdoff delay before the waveform (described by the values of t1~t4) begins as shown in figure 3. the holdoff delay occurs only after 1) any 8-bit value is written to the update register (0ch), or 2) turn on the one shot programming mode by programming the rgb mode register (02h) all output t0 registers (0ah~0fh) are programmed in the same manner. t0 time delay of output current 0000 0s 0001 0.13s 0010 0.26s 0011 0.52s 0100 1.04s 0101 2.08s 0110 4.16s 0111 8.32s 1000 16.64s 1001 33.28s 1010 66.56s table 10 outx_t1&t2 register (10h~15h) bit d7:d5 d4:d1 d0 name t1 t2 - default 000 0000 0 t1: t1 is the time that the output current ramps up to its final value. it is gamma-corrected and consists of 32 steps and the pwm duty cycle is increasing at each step as shown in table 17. t2: t2 is the time the output holds its maximum current. all output t1, t2 registers (10h~15h) are programmed in the same manner. t1 ramping up time 000 0.13s 001 0.26s 010 0.52s 011 1.04s 100 2.08s 101 4.16s 110 8.32s 111 16.64s t2 holding full current time 0000 0s 0001 0.13s 0010 0.26s 0011 0.52s 0100 1.04s 0101 2.08s 0110 4.16s 0111 8.32s 1000 16.64s table 11 outx_t3&t4 register (16h~1bh) bit d7:d5 d4:d1 d0 name t3 t4 - default 000 0000 0 t3: t3 is the time that the output current ramps down from the maximum value to zero. it is gamma-corrected and consists of 32 steps and the pwm duty cycle is reducing at each step as shown in table 17. t4: t4 is the time delay before repeating the next cycle. all output t3, t4 registers (16h~1bh) are programmed in the same manner. t3 ramping down time 000 0.13s 001 0.26s 010 0.52s 011 1.04s 100 2.08s 101 4.16s 110 8.32s 111 16.64s t4 holding off time 0000 0s 0001 0.13s 0010 0.26s 0011 0.52s 0100 1.04s 0101 2.08s 0110 4.16s 0111 8.32s 1000 16.64s 1001 33.28s 1010 66.56s update register (1ch) once configured, the timing parameters, t0 thru t4, may only be changed by modifying the values stored in the timing registers (0ah~1bh), followed by writing any 8-bit value to the update register. the new timing parameters will take effect following the write to the update register. table 12 out7-0_en register ( 1dh) bit d7 d6:d1 d0 name out7_en out6_en: out1_en out0_en default 1 111 111 1 table 13 out9-8_en register ( 1eh) bit d7 d6 d5: d0 name out9_en out8_en - default 1 1 xx xxxx outx_en register controls the on or off state of each output. notice in register 1dh, the msb d7 enables the out7, while the lsb d0 enables the out0; in register 1eh, the msb d7 enables the out9, d6 enables the out8.
IS31FL3189 integrated silicon solution, inc. ? www.issi.com rev.a, 11/14/2011 11 outx_en output states 0 output off 1 output on table 14 top-down_en registers ( 1fh) bit d7:d5 d4 d3: d0 name - top-down_en _________________________ - default 000 0 0000 top-down_en register controls the on or off state of top-down scan mode. this function is designed for the application where constant output current is needed. when IS31FL3189 is working in top-down scan mode, setting d4 of top-down register to ?1? the IS31FL3189 can keep the output always turned on, and the output current range can be set by writing the rc register (d4:d2 of audio input gain register(01h)). top-down_en _________________________ top-down scan mode enable 0 enable 1 disable table 15 rgb gain2 register (20h) bit d7:d2 d1 d0 function - rgb1_c rgb2_c default 000000 0 0 rgb gain2 register makes rgb current on the fifth setting at 17.5ma. d1 rgb1 current setting 1 rgb1 current is set to 17.5ma 0 rgb1 current is set by reg 03h d0 rgb2 current setting 1 rgb2 current is set to 17.5ma 0 rgb2 current is set by reg 03h
IS31FL3189 integrated silicon solution, inc. ? www.issi.com rev.a, 11/14/2011 12 application information initial power-up on initial power-up, the IS31FL3189 registers are reset to their default values, it operates in top-down scan plus audio synchronization mode and the rgb outputs are not enabled. software shutdown the IS31FL3189 device features a shutdown mode. shutdown mode is entered via a write to the configuration register (see table 4). in shutdown mode all of the output current sources are switched off. shutdown mode can either be used as a means to reduce power consumption or for generating a flashing display (repeatedly entering and leaving shutdown mode). note: during shutdown mode the digit-registers maintain their data. constant current the maximum current of out0 ~ out2, out7 ~ out9, are internally set to one of 5 constant current levels (17.5ma, 28.9ma, 38.9ma, 46.7ma or 66.5ma (typical)). the constant current sinks maintain the output current at the programmed level when sinking current. when set to sink 38.9ma, if the voltage at the output pin falls below 0.4v, because of a large led forward voltage (v f ) or falling supply voltage, then the output current will begin to fall off as decrease of headroom voltage. the selection for th e constant current level is made by programming the rgb gain registers as shown in table 7 and table 15. audio synchronization only mode the IS31FL3189 features an audio synchronization only mode where each led driver?s output current is dependent on the audio input signal. the intensity of any given led output is dependent upon the amplitude of the audio signal. an increase in the amplitude of the audio signal will increase the output current of led driver. the audio synchronization only mode allows each led output to react to the amplitude of the audio input signal. audio synchronization only mode is activated by programming the configuration byte bit d7 low and bit d6 high. the IS31FL3189 has one single-ended analog audio input designated in, where voice data, mp3, or fm radio data is routed to in. the gain of the audio input summing amplifier is programmed by the audio input gain register bit d7~d5. increasing the gain of the audio input summing amplifier will increase the intensity of the leds in audio synchronization only mode. when the IS31FL3189 is configured to operate in audio synchronization only mode and the voltage of the output pin is above the minimum headroom voltage, vds headroom voltage, the maximum output current of each channel is dependent upon the value of the external programming resistor, r ext , if the voltage at the output pin is below the minimum headroom voltage, v ds < headroom voltage, the output current will drop to a certain value of current whose headroom is equal to v ds . the maximum output current of each channel is set by an external resistor r ext , as show in figure 4. 10 15 20 25 30 35 300 600 900 1200 1500 1800 2100 r-ext() i out (ma) figure 4 i out vs. r ext when v in = 1.35vp-p sine wave, gain = 12db careful selection of r ext and gain setting is required so as not to exceed output current designed for the system. audio input dc filtering capacitor is absolutely necessary for better signal-to-noise ratio, led output current uniformity and lighting effects. top-down scan mode when the IS31FL3189 is configured to operate in top-down scan mode, the constant current output is programmed by the audio input gain register bit d4~d2. top-down scan mode (1) the IS31FL3189 offers a special lighting effect by controlling the duty cycle and timing of each channel. when rgb mode is enabled, out0~out2 and out7~out9 are controlled by rgb mode register bytes, and out3~out6 will operate as shown below in figure 5 when configuration register d3~d1 are set low. when the configuration register d3~d1 are set different, the scan rate can be changed as the commentary of configuration register.
IS31FL3189 integrated silicon solution, inc. ? www.issi.com rev.a, 11/14/2011 13 t2 t3 t4 t6 t9 t 8 t 7 t 5 t t=0 figure 5 timing of top-down scan mode (1) this waveform describes the output voltage of out3~out6. the output is on when it is low. 0~ ? t, all channels turn off, where ? t is 22ms ? t~2 ? t, out3 turns on, out4~out6 turn off; 2 ? t~3 ? t, out3, out4 turn on, out5 and out6 turn off; ?? 7 ? t~8 ? t, out3 turns on, out4~out6 turn off; then next cycle starts again. top-down scan mode (2) each rgb can be disabled via configuration register bit d4 and bit d5.when rgb mode is disabled, the function of out0~out2 and out7~out9 is the same as out3~out6, operating as described by the waveforms below in figure 6 when the configuration register d3~d1 are set low. figure 6 timing of top-down scan mode (2) constant current mode this mode is based on top-down scan mode and can be enabled by setting d4 of register 1fh in table 14, it can maintain a constant current without scan. the current can be adjusted by programming the current of scan mode, d4:d2 of audio input gain register. audio synchronization plus top-down scan mode when initially powering the ic or if the IS31FL3189 is configured to operate in audio synchronization plus top-down scan mode, the output current is programmed as described in audio synchronization mode section, and the top-down scan rate is set by the configuration register d3~d1. interface intensity control mode when configuration register (00h) d5 and d4 are set high, the maximum current of output is selected via rgb current register (03h) bits d3~d0. outputs operate in interface intensity control mode when you clear the rgb mode register bits d5&d4. in this control mode, you must send data if you want to change the pwm intensity of the rgb leds. the IS31FL3189?s pwm led outputs can be used to drive individual color leds or rgb led modules. when driving an rgb led module, the intensity of each led in the module is programmable allowing the rgb led module to be set to many different colors, based on the value of the pwm byte. when interface intensity control mode is enabled, the average output current of out0~out2, out7~out9, is dependent upon the pwm duty cycle. leds driven with a higher duty cycle results in a higher luminous intensity. for example, if the maximum output current is 38.9ma, the table below gives some average i out values controlled by pwm bytes. the average output current can be adjusted in 256 steps of pwm control. table 16 256 steps output current pmw byte i out (ma) 0x00 0 0x01 0.15 0x02 0.30 0x03 0.46 ? ? ? ? 0xff 38.9 one shot programming mode outputs work in one shot programming mode when you set rgb mode register bits d5&d4 to ?1?. when the IS31FL3189 is operating in one shot programming mode, the output waveform is user configurable by the selection of t0~t4. new values written to t0~t4 will take effect after writing any 8 bits of data to the update register. in one shot programming mode, the pwm duty cycle is defined by t0-t4. t0: t0 is the holdoff delay before the waveform (described by the values of t1~t4) begins as shown in figure 3. the holdoff delay occurs only after 1) any 8-bit value is written to the update register, or 2) turn on the one shot programming mode by programming the rgb mode register (02h) t1: t1 is the time that the output current ramps up to its final value. it consists of 32 steps and the pwm duty cycle is increasing at each step as shown in table 17. t2: t2 is the time the output holds its maximum current. t3: t3 is the time that the output current ramps down
IS31FL3189 integrated silicon solution, inc. ? www.issi.com rev.a, 11/14/2011 14 from the maximum value to zero. it consists of 32 steps and the pwm duty cycle is reducing at each step as shown in table 17. t4: t4 is the time delay before repeating the next cycle. by programming different values of t0~t4 for the different outputs, out0~out2, out7~out9, many different combinations led effects can be created. the complete waveform period consists of the summation of all times t1~t4. table 17 gamma-corrected pwm duty cycle (gamma=1.8) gray scale data duty cycle (1/256) gray scale data duty cycle (1/256) 0 0 16 85 1 1 17 95 2 3 18 105 3 5 19 115 4 8 20 125 5 12 21 136 6 16 22 148 7 21 23 160 8 26 24 172 9 32 25 185 10 38 26 198 11 45 27 211 12 52 28 225 13 60 29 239 14 68 30 254 15 76 31 255
IS31FL3189 integrated silicon solution, inc. ? www.issi.com rev.a, 11/14/2011 15 classification reflow profiles profile feature pb-free assembly preheat & soak temperature min (tsmin) temperature max (tsmax) time (tsmin to tsmax) (ts) 150c 200c 60-120 seconds average ramp-up rate (tsmax to tp) 3c/second max. liquidous temperature (tl) time at liquidous (tl) 217c 60-150 seconds peak package body temperature (tp)* max 260c time (tp)** within 5c of the specified classification temperature (tc) max 30 seconds average ramp-down rate (tp to tsmax) 6c/second max. time 25c to peak temperature 8 minutes max. figure 7 classification profile
IS31FL3189 integrated silicon solution, inc. ? www.issi.com rev.a, 11/14/2011 16 tape and reel information
IS31FL3189 integrated silicon solution, inc. ? www.issi.com rev.a, 11/14/2011 17 package information qfn-20 note: all dimensions in millimeters unless otherwise stated.

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